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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. july 2009 doc id 14860 rev 3 1/47 1 STA680 hd radio? baseband receiver features general hd radio signal decoding for am and fm digital audio tensilica? signal/audio processing core architecture running up to 166 mhz hardware support for conditional access (one-time programmable 640-bit memory) 2 internal plls: processor cores and peripheral bus 1 internal clock oscillator and external clock input 250 mw with core voltage of 1.2 v and io voltage of 3.3 v temperature range: -40 to +85 c memories internal boot rom sdram controller addressing up to 512 mbit of sdram in x16 configuration serial flash memory interface for application code loading turner interface support of rf-if peripheral processor (ripp) and other front ends such as sta3004 and sta7506 input from rf front-end via programmable serial interface supporting 650 ks/s, 675 ks/s, 744.1875 ks/s, 882 ks/s, 912 ks/s sample rates secondary rf front-end interface for dual tuner applications other interfaces one stereo audio sample rate converter (44.1 ks/s, 45.6 ks/s, 48 ks/s) one input and three stereo channels audio output (by iis serial audio interface) 2 iic and 3 spi serial interfaces 1 uart interface 1 gpio interface (8 lines) sd/mmc interface via spi jtag interface supported hd radio system capabilities multicasting program service data real-time traffic audio time shifting itunes tagging? surround sound applications car radio personal navigation device (pnd) portable battery operated systems lqfp144 (20x20x1.4 mm) lfbga 168 balls (12x12x1.4 mm) table 1. device summary order code package (1) 1. ecopack? compliant. packing STA680 lfbga 168 balls (12x12x1.4 mm) tray STA680q lqfp144 (20x20mm) tray www.st.com
contents STA680 2/47 doc id 14860 rev 3 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 hd radio? system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 receiver system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 hd radio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 dual stream hd radio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 additional processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.1 am/fm processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.2 audio codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.3 other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 overview of main functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.1 adjacent channel filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.2 hifi2 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.3 vectra core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.4 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.5 hardware accelerator (viterbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 i/o description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 lqfp description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 lfbga description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 i/os supply groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 operation and general remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 clock schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.1 power supply ramp up phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.2 oscillator setting time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.3 boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.4 normal operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 digital i/o and memory interf aces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 interfaces: lqfp vs. lfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STA680 contents doc id 14860 rev 3 3/47 6.2 tuner interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 audio interface (aif) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3.1 output serial audio interface (sai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3.2 input serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.3 s/pdif interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.4 audio sample rate converter (asrc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 serial peripheral interfaces (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4.1 host micro serial peripheral interface (spi1) . . . . . . . . . . . . . . . . . . . . . 34 6.4.2 flash serial peripheral interface (spi2) . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.3 sd/mmc serial peripheral interface (spi3) . . . . . . . . . . . . . . . . . . . . . . 35 6.4.4 i 2 c interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.5 host micro i 2 c interface (i2c1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.4.6 auxiliary i 2 c interface (i2c2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5 sdram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
list of tables STA680 4/47 doc id 14860 rev 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. reference clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 4. power on timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5. interface list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. baseband interfaces pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. bbi timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8. aif pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9. serial audio interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. spi interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. host micro spi pin list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 12. flash spi pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 13. sd/mmc spi pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 14. host and auxiliary i 2 c interface pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 15. i 2 c interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 16. i2c1 interface device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. i2c2 interface device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. sdram interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. sdram interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 20. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 21. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 22. dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 23. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STA680 list of figures doc id 14860 rev 3 5/47 list of figures figure 1. functional data flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. hd radio? system logo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. STA680 block diagram (detailed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. single channel application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. dual channel application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. lqfp pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. lfbga ballout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. power on timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. crystal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. bbi waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12. serial audio interface waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 13. spi interface timings diagrams and waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14. timing diagrams and waveform for the two i 2 c interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15. timing diagrams and waveform for the sdram interface . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 16. lqfp144 (20x20mm) mechanical data and packa ge dimensions . . . . . . . . . . . . . . . . . . . 44 figure 17. lfbga 168 balls (12x12x1.4 mm) mechanical data and package dimensions . . . . . . . . . 45
description STA680 6/47 doc id 14860 rev 3 1 description the STA680 from stmicroelectronics is a system on a chip designed for demodulating and decoding of hd radio (a) signals. the STA680 is compliant with the ibiquity specification and extends the possibility to implement new and op tional features and to manage additional services. the device combines it all into a single ic consisting of several hardware blocks and a programmable core to guarantee the proper level of flexibility, low current consumption and an optimized die size. the STA680 implements the entire signal pr ocessing chain of an hd radio receiver. the digital channel demodulation and decoding, including ofdm demodulation and error correction. source decoding, consisting of audio and data decoding of the digital channel. the analog demodulator extracting the audio signal from the legacy analog am/fm signal (can be implemented as an optional feature) the blending of the analog and digital audio signals figure 1 presents a functional diagram describing the data flow inside STA680 for hd radio demodulating and decoding. the architecture consists of an effective and balanced hardware/software implementation, to pursue the best co mbination in terms of current consumption, system flexibility and device cost. functional blocks which are standard, and co mputation intensive, are implemented using custom logic. software implemen tation is more efficient for functional blocks where flexibility is needed. such flexibilit y enables the STA680 to be ready for future evolution, and allows the implementation of specific and optional features. figure 1. functional data flow diagram a. hd radio? technology manufactured und er license from ibiquity digital corp. u.s. and foreign patents. hd radio? and the hd radio logo are proprietary trademarks of ibiquity digital corp. ac00175 src main bb interface src main bb interface src secondary bb interface src secondary bb interface ofdm demod psk/qam demod deinterleaver and convolutional decoding channel decoder ofdm demod psk/qam demod deinterleaver and convolutional decoding channel decoder digital digital analog am/fm demodulation demux hdc decoder data processing source decoder blending blended audio sample rate converter and serial interfaces audio samples data i2s spi i2c bbi1 bbi2 i2s * * * this features may be performed outside STA680 depending on the software configuration legacy am/fm samples STA680
STA680 hd radio? system doc id 14860 rev 3 7/47 2 hd radio? system the hd radio? system, compliant with na tional radio system committee nsrc-5 standard, was developed by ibiquity digital corporation. this system is designed to permit a smooth evolution from current (legacy) analog am/fm radio to a fully digital in-band on-channel (iboc) system. the hd radio system delivers digital audio and data services to mobile, portable, and fixed receivers from terrestrial trasmitters in the existing medium frequency (mf) and very high frequency (vhf) radio bands. broadcaster may continue to transmit analog am and fm simultaneusly with the new, higher quality and more robust digital signal, allowing themselves and their listener to convert from legacy analog to digital radio while maintaining their current frequencies allocations. the hd radio system is identified by the logo reported hereafter: figure 2. hd radio? system logo
receiver system overview STA680 8/47 doc id 14860 rev 3 3 receiver system overview figure 3 shows the partitioning of the hd radio receiver system, composed by an am/fm rf front-end, if channel signal processor and the hd radio decoder (STA680). figure 3. STA680 block diagram (detailed) the analog if signal from the tuner front-end is digitized by a high-resolution sigma-delta a/d converter. a digital down-converter block, embedded into the if channel signal processor, transforms the if into a complex baseband signal. its bandwidth and sample rate have been adapted by filtering and decimation to match the specification of the hd radio system. the complex baseband signal feed the hd radio decoder (STA680) where the hd radio stream is demodulated and decoded. the STA680 receives a digital baseband signal from the if channel signal processor and returns the recovered audio and data services. STA680 can be configured to work with digital if baseband inputs based on standard front- ends. front-ends must conform to hd radio standards for filter bandwidth and linearity. the STA680 requires external serial flash memory to boot but can also be configured to boot from a host controller on iic or spi interfaces. the flash memory is issued for program code and configuration data storage. STA680 needs sdram for bulk data storage required during the iboc signal processing. core system i/o & control interface bbi 1 i2s am/fm baseband tuner (i.e. sta3004) rf tuner (i.e. tda7528) baseband interface peripheral bus ahb bus audio interface vectra lx tensilica dsp hifi tensilica core viterbi dma spi flash spi sd/mmc gpio clock gen. unit system pll peripheral pll ldo crystal oscillator opt. xtal 28.224 mhz STA680 ahb/apb bridge slave connection master connection 1mb serial flash (bootable) 8 mbit (1mx8) mmc,sd sdio cards (4/8bit) mmc,sd sdio cards (4/8bit) main micro sdram interface 8mb sdram 64 mbit (4mx16) otp spi/i2c micro i/f boundary scan jtag tuner & audio interface bbi 2
STA680 receiver system overview doc id 14860 rev 3 9/47 3.1 hd radio processing the STA680 hd radio decoder does the proce ssing of the iboc signal. it receives a complex digital signal from an am/fm if channel signal processor. the native sample rate is 744.1875 ks/s for fm and 46.51171875 ks/s for am. however, other input sample rates are acceptable because of the sample rate converter in the baseband interface (bbi). these include: 650 ks/s, 675 ks/s, 882 ks/s and 912 ks /s. if a baseband signal is provided that is not at the native sample frequency of 744.1875 khz it must be sample rate converted to this rate. sample rate conversion hardware is provided on-chip to support this. this feature allows the STA680 to operate with various am/fm front-ends. the STA680is then responsible for detection, acquisition, and demodulation of the iboc signal. such function is primarily implemen ted by the vectra dsp core. the demodulated signal is then passes to the hi-fi processor, for decoding, audio blending and handling of data services. a digital 44.1 khz decompressed audio is output via the digital audio interface. the STA680 uses sophisticated algorithms to re cover iboc data even in the presence of signal impairments including fading and a variety of other interferences. to process the hd radio stream STA680 requires a 4m x16 external sdram (with up to 32m x16 supported) for data storage. 3.2 dual stream hd radio processing STA680 is capable to simultaneously demodulate two different hd radio streams. this unique feature enables the device to decode an hd radio audio stream, in parallel with any data service broadcasted by a different radi o channel. the implementation of the dual stream hd radio processing requires that two am/fm rf tuners are connected to the STA680. in a single channel implementation a single rf tuner is used. in such configuration STA680 is able to demodulate at the same time both the audio and the data associated with the radio channel (i.e. 92.5 mhz or 102.5 mhz). this means that if the user sets the tuner 102.5 mhz, he or she can listed to fm2 audio and receive traffic information broadcasted on that channel. at the same time if the user tunes to another frequency (fm1), current traffic information will be lost. figure 4. single channel application STA680 is able to demodulate both audio and data associated with a single radio channel. example: while receiver is tuned to 99.5mhz, it is possible to simultaneously listen to audio content and receive traffic information associated with this channel. fm1 audio fm1 news fm 1 fm1 audio fm1 news fm 1 fm2 audio fm2 traffic fm 2 fm2 audio fm2 traffic fm 2 92.5 95.5 mhz data received is bound to the selected audio channel or or fm1 audio fm2 audio 95.5 traffic 92.5 news
receiver system overview STA680 10/47 doc id 14860 rev 3 in a dual channels implementation STA680 can simultaneously demodulate audio and data associated to different radio channels. this means that in the example above it would be still possible to receive traffic information broadcasted on fm2 (102.5 mhz) while listening fm1 audio program broadcasted on 92.5 mhz figure 5. dual channel application 3.3 additional processing the hd radio stream demodulation and decoding take up only part of the computation power and memories resources available on STA680. this makes it possible to use the spare resources to implement additional features. depending on memory and computation power required by the additional features, it is possible to run them in parallel with the hd radio stream decoding or in alternative, having all the hardware resources available for the additional features. 3.3.1 am/fm processing it is possible to implement legacy am/fm processing in parallel with the hd radio stream demodulation and decoding. such solution is particularly suitable and appealing when the STA680 processor works jointly with an am/fm rf front-end not incorporating the am/fm demodulation. 3.3.2 audio codec STA680 can be used as a media processor to decode mp3/wma audio stream. thanks to the availability of the mmc and sd interface it is possible to reproduce an mp3 stream stored into any mmc or sd cards fm1 audio fm1 news fm 1 fm1 audio fm1 news fm 1 fm2 audio fm2 traffic fm 2 92.5 95.5 mhz audio and data can belong to different channels or or in this configuration, the system is able to simultaneously demodulate audio and data from the first radio channel plus data from a second one. as a result STA680 can provide 1 audio and 2 data channels. alternatively it is possible to receive audio content from one channel while pulling traffic or weather data from another at the same time. fm1 audio fm2 audio 92.5 news 95.5 traffic 92.5 news 95.5 traffic
STA680 receiver system overview doc id 14860 rev 3 11/47 3.3.3 other the spare computation power and memories are suitable to implement other specific algorithms or custom software application. for example sophisticated sound and audio processing could be implemented on the hd radio decompressed audio. audio output can be provided either in iis master clock mode or in slave mode with the on-chip audio sample rate converter. up to six audio channels may be provided in a standard configuration. another possibility is to im plement on the STA680 the handling of data services. 3.4 overview of main functional blocks 3.4.1 adjacent channel filter this module performs time doma in filtering specifically for iboc system. it receives a complex baseband iboc signal input from src module and pre-conditions the signal for subsequent modem processing. the module is a front-end device. 3.4.2 hifi2 core the hifi2 is a signal processing engine specif ically designed to provide high quality 24-bit audio processing. the hifi2 is also useful for advanced data applications such as storage and playback of received audio and conditional access processing. the hifi2 leverages the tensilica xtensa lx engine with additional usef ul hardware capabilities such as: specialized instructions for 24-bit audio mac & stream coding dual mac (each supports 24 x 24 and 32 x 16 bit format) huffman encode / decode and truncate functions two way simd arithmetic and boolean operations 3.4.3 vectra core the vectra lx is a powerful, configurable 32-bit risc engine optimized for dsp with vliw capabilities. the vectra lx on board the STA680 includes eight mac units, sixteen 160-bit vector operation registers, and a number of simd arithmetic instructions. custom instructions in the vectra are targeted for dsp applications such as filters and ffts. the vectra processor has been further configured with specific instructions for efficient performance on the hd radio application. 3.4.4 dma a ten-channel dma controller is attached to the ahb bus to allow the vectra and hifi2 processor cores to move large blocks of data efficiently. certain channels are dedicated for use with certain hardware blocks because of hardware handshaking signals. 3.4.5 hardware accelerator (viterbi) a complex convolutional viterbi module is de signed to fully comply with the hd radio system. the module supports both k constant of 7 and 9, for iboc digital fm and am bands respectively.
i/o description STA680 12/47 doc id 14860 rev 3 4 i/o description the STA680 has two package options to suit different application needs. the first option is a 20x20mm lqfp package with 144 pins while the second one is a 12x12mm lfbga with 169 balls and 0.8mm pitch. 4.1 lqfp description figure 6 presents the pinout of the STA680 for the lqfp package option. different colors have been used for i/o signals from different interfaces according to ta b l e 2 reported in section 4.3 . figure 6. lqfp pinout (top view) vdd vdd gnd sdr_a3 sdr_a2 sdr_a1 sdr_a0 sdr_a10 gnd_ram_io vdd_ram_io sdr_ba1 sdr_ba0 sdr_cs_n gnd vdd sdr_ras_n sdr_cas_n sdr_we_n sdr_a4 gnd_ram_io vdd_ram_io sdr_a5 sdr_a6 sdr_a7 gnd vdd sdr_a8 sdr_a9 sdr_a11 sdr_a12 gnd_ram_io vdd_ram_io sdr_cke sdr_dqm1 sdr_dqm0 gnd sdr_d7 sdr_d6 sdr_d5 vdd_ram_io gnd_ram_io sdr_d4 sdr_d3 sdr_d2 vdd gnd sdr_d1 sdr_d0 sdr_d8 sdr_d9 vdd_ram_io gnd_ram_io sdr_d10 sdr_d11 sdr_d12 vdd gnd sdr_d13 sdr_d14 sdr_d15 sdr_feed_clk sdr_clk_ram3v3 gnd_ram_io_1v8 vdd_ram_io_1v8 gnd vdd spi2_ss1_n spi2_miso spi2_sck spi2_ss0_n spi2_mosi vdd_fsh_io gnd gnd_gen_io vdd_gen_io bb1_i bb1_ws bb1_bck spdif audio_in_abck audio_in_aws vdd gnd gnd_gen_io vdd_gen_io audio_in_adat dac256x adat3 adat2 adat aws abck clk_in gnd vdd gnd_pll_dig vdd_pll_dig gnd_pll0_ana vdd_pll0_ana gnd_osc vdd_osc osc_in osc_out vdd_reg3v3 vdd_reg1v8 gnd vdd gnd_fsh_io 144 143 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 1 108 2 107 3 106 4 105 5 104 6 103 7 102 8 101 9 100 10 99 11 98 12 97 13 96 14 95 15 94 16 93 17 92 18 91 19 90 20 89 21 88 22 87 23 86 24 85 25 84 26 83 27 82 28 81 29 80 30 79 31 78 32 77 33 76 34 75 35 74 36 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 142 testmode trst_n tck tms tdi tdo rts_gpio0 vdd gnd cts_gpio1 gnd_gen_io vdd_gen_io txd_gpio2 rxd_gpio3 reset_n spi1_ss0_n spi1_sck spi1_mosi vdd gnd spi1_miso gnd_gen_io vdd_gen_io iic1_scl iic1_sda bb2_q gnd vdd gnd_gen_io vdd_gen_io bb2_i bb2_ws bb2_bck blend bb1_q vdd ac00504 color legend: sdram interfaces iis tuner interfaces flash/card interfaces host processor interfaces gpio & uart interfaces iis audio input interfaces audio output interfaces
STA680 i/o description doc id 14860 rev 3 13/47 4.2 lfbga description figure 7 presents the ballout of the STA680 for the lfbga package option. different colors have been used for i/o signals from different interfaces according to ta b l e 2 reported in section 4.3 . figure 7. lfbga ballout (top view) 1234567891011121314 a b c d e f g h j k l m n p gpio6 bb2_bck bb2_i gnd_io_gen iic1_sda spi1_miso spi1_sck reset_n txd_gpio2 rts_gpio0 vdd_gen_io testmode gpio5 bb1_q blend bb2_ws gnd_io_gen bb2_q iic1_scl spi1_mosi spi1_ss0_n rxd_gpio3 cts_gpio1 vdd_gen_io sdr_a3 sdr_a3 trst_n trst_n bb1_ws bb1_i adat2 iic2_sda gpio7 iic2_scl iic1_da spi3_mosi spi3_miso spi3_sck tdi tck sdr_a1 sdr_a1 sdr_a2 sdr_a2 vdd_gen_io vdd_gen_io bb1_bck iic2_da vdd vdd spi3_ss_n gpio4 tdo tms sdr_a10 sdr_a10 sdr_a0 sdr_a0 audio_in_ abck spdif adat3 vdd_pll_dig vdd modeop_fsh sdr_ba0 sdr_ba0 sdr_ba1 sdr_ba1 audio_in_ adat audio_in_ aws gnd_pll_ dig gnd_pll_ dig gnd gnd gnd gnd vdd modeop_gen sdr_ras_n sdr_ras_n sdr_cs_n sdr_cs_n aws adat dac256x gnd gnd gnd gnd sdr_cas_n sdr_cas_n sdr_we_n sdr_we_n vdd_ram_io vdd_ram_io gnd_io_gen gnd_io_gen abck gnd gnd gnd gnd sdr_a4 sdr_a4 sdr_a5 sdr_a5 gnd_ram_io gnd_ram_io vdd_osc gnd_osc gnd_pll1_ ana gnd_pll0_ ana gnd gnd gnd gnd vdd vdd sdr_a7 sdr_a7 sdr_a6 sdr_a6 osc_out clk_in vdd vdd_reg3v3 vdd vdd sdr_a9 sdr_a9 sdr_a8 sdr_a8 osc_in gnd_osc vdd vdd_reg3v3 vdd_fsh_io gnd_fsh_io vdd_ram_io _1v8 gnd_ram_io _1v8 gnd_ram_io gnd_ram_io sdr_a12 sdr_a12 sdr_a11 sdr_a11 vdd_pll1_ ana vdd_pll0_ ana spi2_ss1_n spi2_ss2_n spi2_ss3_n rfu sdr_d13 sdr_d10 vdd_ram_io vdd_ram_io gnd_ram_io gnd_ram_io sdr_dqm1 sdr_cke vdd_reg1v8 vdd_reg1v8 spi2_mosi spi2_sck sdr_clk_ ram3v3 sdr_d15 sdr_d15 sdr_d12 sdr_d12 sdr_d9 sdr_d9 sdr_d0 sdr_d0 sdr_d2 sdr_d2 sdr_d4 sdr_d4 sdr_d6 sdr_d6 sdr_dqm0 spi2_ss0_n spi2_miso sdr_feed_ clk sdr_d14 sdr_d14 sdr_d11 sdr_d11 sdr_d8 sdr_d8 sdr_d1 sdr_d1 sdr_d3 sdr_d3 sdr_d5 sdr_d5 sdr_d7 sdr_d7 ball unused ball not present ac0070 7 color legend: sdram interfaces iis tuner interfaces flash/card interfaces host processor interfaces gpio & uart interfaces iis audio input interfaces audio output interfaces
i/o description STA680 14/47 doc id 14860 rev 3 4.3 pin list the ta bl e 2 briefly describes the main function and characteristics of the STA680 i/o signals in normal operation mode. table 2. pins description pin # ball # signal name type pull-up /down (1) electrical supply group description test 1 a13 testmode i pull-down 1.8 v or 3.3 v generic io supply factory test mode enable standard 1149.1 jtag interface 2 b14 trst_n i pull-up 1.8 v or 3.3 v generic io supply jtag active-low test reset 3 c12 tck i pull-down 1.8 v or 3.3 v generic io supply jtag test clock 4 d12 tms i pull-up 1.8 v or 3.3 v generic io supply jtag test mode state 5 c11 tdi i pull-up 1.8 v or 3.3 v generic io supply jtag test data in 6 d11 tdo o - 1.8 v or 3.3 v generic io supply jtag test data out gpio & uart interfaces 7a11 rts_gpio0 i/o pull-up 1.8 v or 3.3 v generic io supply uart ready to send / gpio bit 0 10 b11 cts_gpio1 i/o pull-up 1.8 v or 3.3 v generic io supply uart clear to send / gpio bit 1 13 a10 txd_gpio2 i/o pull-up 1.8 v or 3.3 v generic io supply uart transmit data / gpio bit 2 14 b10 rxd_gpio3 i/o pull-up 1.8 v or 3.3 v generic io supply uart receive data / gpio bit 3 not bonded d10 gpio4 i/o pull-up 1.8 v or 3.3 v generic io supply gpio bit 4 not bonded b1 gpio5 i/o pull-up 1.8 v or 3.3 v generic io supply gpio bit 5 not bonded a2 gpio6 i/o pull-up 1.8 v or 3.3 v generic io supply gpio bit 6 not bonded c5 gpio7 i/o pull-up 1.8 v or 3.3 v generic io supply gpio bit 7 reset 15 a9 reset_n i pull-up 1.8 v or 3.3 v generic io supply device active-low reset
STA680 i/o description doc id 14860 rev 3 15/47 host processor interfaces 16 b9 spi1_ss0_n i pull-up 1.8 v or 3.3 v generic io supply spi interface 1 active-low slave select 17 a8 spi1_sck i pull-up 1.8 v or 3.3 v generic io supply spi interface 1 serial clock 18 b8 spi1_mosi i pull-up 1.8 v or 3.3 v generic io supply spi interface 1 serial data master out/slave in 21 a7 spi1_miso o pull-up 1.8 v or 3.3 v generic io supply spi interface 1 serial data master in/slave out 24 b7 iic1_scl i/o pull-up 1.8 v or 3.3 v generic io supply iic interface 1 serial clock line 25 a6 iic1_sda i/o pull-up 1.8 v or 3.3 v generic io supply iic interface 1 serial data line not bonded c7 iic1_da i/o pull-up 1.8 v or 3.3 v generic io supply iic interface 1 data acknowledged not bonded c6 iic2_scl i/o pull-up 1.8 v or 3.3 v generic io supply iic interface 2 serial clock line not bonded c4 iic2_sda i/o pull-up 1.8 v or 3.3 v generic io supply iic interface 2 serial data line not bonded d4 iic2_da i/o pull-up 1.8 v or 3.3 v generic io supply iic interface 2 data acknowledged iis tuner interfaces 40 c2 bb1_i i pull-down 1.8 v or 3.3 v generic io supply primary baseband interface serial i data 35 b2 bb1_q i pull-down 1.8 v or 3.3 v generic io supply primary baseband interface serial q data 41 c1 bb1_ws i pull-down 1.8 v or 3.3 v generic io supply primary baseband interface word strobe 42 d3 bb1_bck i pull-down 1.8 v or 3.3 v generic io supply primary baseband interface bit clock 31 a4 bb2_i i pull-down 1.8 v or 3.3 v generic io supply secondary baseband interface serial i data 26 b6 bb2_q i pull-down 1.8 v or 3.3 v generic io supply secondary baseband interface serial q data 32 b4 bb2_ws i pull-down 1.8 v or 3.3 v generic io supply secondary baseband interface word strobe 33 a3 bb2_bck i pull-down 1.8 v or 3.3 v generic io supply secondary baseband interface bit clock table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description
i/o description STA680 16/47 doc id 14860 rev 3 iis audio input interface 45 f2 audio_in_aws i pull-up 1.8 v or 3.3 v generic io supply digital audio input word strobe 44 e1 audio_in_abck i pull-up 1.8 v or 3.3 v generic io supply digital audio input bit clock 50 f1 audio_in_adat i pull-down 1.8 v or 3.3 v generic io supply digital audio input serial data audio output interfaces 55 g1 aws i/o pull-up 1.8 v or 3.3 v generic io supply digital audio output word strobe 56 h3 abck i/o pull-up 1.8 v or 3.3 v generic io supply digital audio output clock 54 g2 adat o - 1.8 v or 3.3 v generic io supply digital audio output serial data 53 c3 adat2 o - 1.8 v or 3.3 v generic io supply digital audio output serial data channel 2 52 e3 adat3 o - 1.8 v or 3.3 v generic io supply digital audio output serial data channel 3 43 e2 spdif o - 1.8 v or 3.3 v generic io supply digital audio output in spdif format 34 b3 blend o - 1.8 v or 3.3 v generic io supply digital audio output blend output 51 g3 dac256x o - 1.8 v or 3.3 v generic io supply digital audio output oversampling clock clock & oscillator 57 k2 clk_in i - 1.8 v or 3.3 v generic io supply reference digital clock 66 l1 osc_in ana - 1.8 v osc supply 28,224mhz crystal in or digital clock input 67 l2 osc_out ana - 1.8 v osc supply crystal output spi flash interface 78 p4 spi2_miso i pull-up 1.8 v or 3.3 v flash io supply spi interface 2 serial data master in/slave out 74 n3 spi2_mosi o pull-up 1.8 v or 3.3 v flash io supply spi interface 2 serial data master out/slave in 75 p3 spi2_ss0_n o pull-up 1.8 v or 3.3 v flash io supply spi interface 2 active-low slave select 0 table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description
STA680 i/o description doc id 14860 rev 3 17/47 77 m3 spi2_ss1_n o pull-up 1.8 v or 3.3 v flash io supply spi interface 2 active-low slave select 1 not bonded m4 spi2_ss2_n o pull-up 1.8 v or 3.3 v flash io supply spi interface 2 active-low slave select 2 not bonded m5 spi2_ss3_n o pull-up 1.8 v or 3.3 v flash io supply spi interface 2 active-low slave select 3 76 n4 spi2_sck o pull-up 1.8 v or 3.3 v flash io supply spi interface 2 serial clock spi sd/mmc interface not bonded c9 spi3_miso i pull-up 1.8 v or 3.3 v generic io supply spi interface 3 serial data master in/slave out not bonded c8 spi3_mosi o pull-up 1.8 v or 3.3 v generic io supply spi interface 3 serial data master out/slave in not bonded d9 spi3_ss_n o pull-up 1.8 v or 3.3 v generic io supply spi interface 3 active-low slave select not bonded c10 spi3_sck o pull-up 1.8 v or 3.3 v generic io supply spi interface 3 serial clock sdram interface 84 p5 sdr_feed_clk i - 3.3 v sdram io supply feedback clock from sdram interface 83 n5 sdr_clk_ram 3v3 o - 3.3 v sdram io supply clock to sdram for 3.3 v interface 97 n9 sdr_d0 i/o - 3.3 v sdram io supply sdram bidirectional data bit 0 98 p9 sdr_d1 i/o - 3.3 v sdram io supply sdram bidirectional data bit 1 101 n10 sdr_d2 i/o - 3.3 v sdram io supply sdram bidirectional data bit 2 102 p10 sdr_d3 i/o - 3.3 v sdram io supply sdram bidirectional data bit 3 103 n11 sdr_d4 i/o - 3.3 v sdram io supply sdram bidirectional data bit 4 106 p11 sdr_d5 i/o - 3.3 v sdram io supply sdram bidirectional data bit 5 107 n12 sdr_d6 i/o - 3.3 v sdram io supply sdram bidirectional data bit 6 108 p12 sdr_d7 i/o - 3.3 v sdram io supply sdram bidirectional data bit 7 96 p8 sdr_d8 i/o - 3.3 v sdram io supply sdram bidirectional data bit 8 table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description
i/o description STA680 18/47 doc id 14860 rev 3 95 p9 sdr_d9 i/o - 3.3 v sdram io supply sdram bidirectional data bit 9 92 m8 sdr_d10 i/o - 3.3 v sdram io supply sdram bidirectional data bit 10 91 p7 sdr_d11 i/o - 3.3 v sdram io supply sdram bidirectional data bit 11 90 n7 sdr_d12 i/o - 3.3 v sdram io supply sdram bidirectional data bit 12 87 m7 sdr_d13 i/o - 3.3 v sdram io supply sdram bidirectional data bit 13 86 p6 sdr_d14 i/o - 3.3 v sdram io supply sdram bidirectional data bit 14 85 n6 sdr_d15 i/o - 3.3 v sdram io supply sdram bidirectional data bit 15 111 n13 sdr_dqm0 o - 3.3 v sdram io supply low-byte data input/output mask 112 m13 sdr_dqm1 o - 3.3 v sdram io supply high-byte data input/output mask 128 g13 sdr_we_n o - 3.3 v sdram io supply active-low write enable 129 g12 sdr_cas_n o - 3.3 v sdram io supply active-low column address strobe 130 f13 sdr_ras_n o - 3.3 v sdram io supply active-low row address strobe 113 m14 sdr_cke o - 3.3 v sdram io supply clock enable 133 f14 sdr_cs_n o - 3.3 v sdram io supply active-low chip select 134 e13 sdr_ba0 o - 3.3 v sdram io supply bank select address 0 135 e14 sdr_ba1 o - 3.3 v sdram io supply bank select address 1 139 d14 sdr_a0 o - 3.3 v sdram io supply address bit 0 to sdram 140 c13 sdr_a1 o - 3.3 v sdram io supply address bit 1 to sdram 141 c14 sdr_a2 o - 3.3 v sdram io supply address bit 2 to sdram 142 b13 sdr_a3 o - 3.3 v sdram io supply address bit 3 to sdram table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description
STA680 i/o description doc id 14860 rev 3 19/47 127 h12 sdr_a4 o - 3.3 v sdram io supply address bit 4 to sdram 124 h13 sdr_a5 o - 3.3 v sdram io supply address bit 5 to sdram 123 j14 sdr_a6 o - 3.3 v sdram io supply address bit 6 to sdram 122 j13 sdr_a7 o - 3.3 v sdram io supply address bit 7 to sdram 119 k14 sdr_a8 o - 3.3 v sdram io supply address bit 8 to sdram 118 k13 sdr_a9 o - 3.3 v sdram io supply address bit 10 to sdram 138 d13 sdr_a10 o - 3.3 v sdram io supply address bit 10 to sdram 117 l14 sdr_a11 o - 3.3 v sdram io supply address bit 11 to sdram 116 l13 sdr_a12 o - 3.3 v sdram io supply address bit 12 to sdram supplies not bonded f12 modeop_gen i pull-up 3.3 v sdram io supply define the opereting voltage of the "generic i/o" supply group. if tied low the i/os work at 1.8v else they work at 3.3v. default value is 3.3v. not bonded e12 modeop_fsh i pull-up 3.3 v sdram io supply define the opereting voltage of the "flash i/o" supply group. if tied low the i/os work at 1.8v else they work at 3.3v. default value is 3.3v. 8, 19, 28, 36, 46, 59, 71, 79, 89, 100, 109, 120, 131, 144 d5, d6, e11, f11, j11, j12, k3, k11, k12, l3 vdd n/a - 1.2 v core supply p ower supply for core logic table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description
i/o description STA680 20/47 doc id 14860 rev 3 9, 20, 27, 37, 47, 58, 70, 80, 88, 99, 110, 121, 132, 143 f6, f7, f8, f9, g6, g7, g8, g9, h6, h7, h8, h9, j6, j7, j8, j9 gnd n/a - - core supply ground for core logic 11, 22, 29, 38, 48 a5, b5, h1, h2 gnd _gen_io n/a - - generic io supply generic i/os ground 12, 23, 30, 39, 49 a12, b12, d1, d2 vdd_gen_io n/a - 1.8 v or 3.3 v generic io supply generic i/os p ower supply 72 l6 gnd _fsh_io n/a - - flash io supply g round for flash interface i/os 73 l5 vdd_fsh_io n/a - 1.8 v or 3.3 v flash io supply p ower supply for flash inteface i/os 93, 104, 115, 126, 137 h14, l11, l12, m11, m12 gnd_ram_io n/a - - sdram io supply g round for sdram interface i/os 94, 105, 114, 125, 136 g14, m9, m10 vdd_ram_io n/a - 3.3 v sdram io supply p ower supply for sdram interface i/os 60 f3, f4 gnd_pll_dig n/a - - pll digital supply g round for pll digital part 61 e4 vdd_pll_dig n/a - 1.2 v pll digital supply p ower supply for pll digital part 62 j4 gnd_pll0_ana n/a - - pll analog supply g round for pll0 analog part (2) 62 j3 gnd_pll1_ana n/a - - pll analog supply g round for pll1 analog part (2) table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description
STA680 i/o description doc id 14860 rev 3 21/47 63 m2 vdd_pll0_ana n/a - 1.8 v pll analog supply p ower supply for pll0 analog part (3) 63 m1 vdd_pll1_ana n/a - 1.8 v pll analog supply p ower supply for pll1 analog part (3) 64 j2, l2 gnd_osc n/a - - osc supply g round for oscillator core 65 j1 vdd_osc n/a - 1.8 v osc supply p ower supply for oscillator core 68 k4, l4 vdd_reg3v3 n/a - 3.3 v ldo supply voltage regulator input power supply@ 3.3 volt 69 n1, n2 vdd_reg1v8 n/a - 1.8 v ldo supply voltage regulator output power supply@1.8 volt 82 l9 vdd_ram_io _1v8 n/a - 1.8 v n/a reserved - connect to 1.8 v supplyt 81 l10 gnd_ram_io _1v8 n/a - - n/a reserved - connect to ground others not bonded m6 rfu n/a - n/a n/a reserved for future use - do not connect 1. each input pin has a pull-up/down resistor to its default value. unless otherwise specified, unused pins can be left unconnected after verifying that the impedance value of the pull-up/down resistor (see table 22 ) is sufficient to guarantee noise immunity in user application environment. 2. in the lqfp package gnd_pll0_ana and gnd_pll1_ana are bonded together. 3. in the lqfp package vdd_pll0_ana and vdd_pll1_ana are bonded together. table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description
i/o description STA680 22/47 doc id 14860 rev 3 4.4 i/os supply groups the STA680 i/o signals are arranged into three different supply groups: generic io supply, flash io supply and sdram io supply group (see ta bl e 2 ). in the lqfp package option all three groups must be supplied with 3.3 v. in the lfbga package the three supply groups can independently operate at 3.3 v or 1.8 v. the sdram_io supply group must always be supplied at 3.3 v. the modeop_gen pin selects the operating voltage of the generic_io supply group. if it is shorted to ground then all the i/o signals belonging to the generic_io supply group will work at 1.8 v; if the modeop_gen pin is left floating or it is tied high (3.3 v) all the group i/os will operate at 3.3 v. the modeop_fsh pin selects the operating voltage of the flash_io supply group. if it is shorted to ground then all the i/o sign als belonging to the flash_io supply group will work at 1.8 v; if the modeop_fsh pin is left floating or it is tied high (3.3 v) the flash interface i/os will operate at 3.3 v.
STA680 operation and general remarks doc id 14860 rev 3 23/47 5 operation and general remarks 5.1 clock schemes the STA680 needs an external clock source to feed the internal phase locked loops (plls) to generate all the frequency needed by its cores and peripherals. this reference clock may be supplied in several ways thus offering flexibility in the development of the final application: the reference clock may be supplied through the use of an external crystal or as a digital signal coming from an external ic. the reference clock may have different frequencies and can be fed to the STA680 through different input pins. the selection of the clock input mode is performed during the power-on phase of the device by latching the value of the pins adat3, blend and dac256x on the rising edge of the reset_n signal (see chapter 5.2 ); this value shall be selected according to ta b l e 3 . table 3. reference clock configuration [adat3, blend, dac256x] clock type input pin clock frequency (mhz) [0,0,0] (1) 1. default setting. crystal osc_in 28.224 [0,0,1] digital osc_in or clk_in (2) 2. when using osc_in pin to input the reference cloc k the clk_in pin must be connected to ground and vice versa. 23.3472 [0,1,0] digital osc_in or clk_in (2) 36.48 [0,1,1] digital osc_in or clk_in (2) 2.9184 [1,0,0] digital bb1_bck 10.4 [1,0,1] digital bb1_bck 10.8 [1,1,0] digital bb1_bck 14.112 [1,1,1] digital audio_in_abck 2.9184
operation and general remarks STA680 24/47 doc id 14860 rev 3 figure 8 shows a simplified version of the internal clock generation unit. figure 8. clock generation unit some remarks on the choice of the clock input pin must be done: osc_in is always a 1.8 v input pin. clk_in, bb1_bck and audio_in_abck are 3.3 v pins when the lqfp package is selected while they can be configured as a 3.3 v or 1.8 v pins if the lfbga is chosen (see chapter 4.4 ) when the clock is fed through clk_in pi n, the osc_in pin must be connected to ground. similarly if the clock is fed using clk_in pin then the osc_in pin must be connected to ground. the bb1_bck pin is the bit clock of the digital interface to the baseband tuner, so to fed the reference clock through this pin the selected clock frequency must be chosen accordingly to the primary baseband interface settings (see chapter 6.2 ): ? 10.4 mhz = 16 * 2 * 650 khz bbi set to 650 ksample/s ? 10.8 mhz = 16 * 2 * 675 khz bbi set to 675 ksample/s ? 14.112 mhz = 16 * 2 * 882 khz bbi set to 882 ksample/s the audio_in_abck is the bit clock of the digital audio input interface to the tuner. when this pin is selected as clock source the STA680 input serial audio interface (see chapter 6.3.2 ) must be set according to following specification: ?slave mode ? input sample rate = 45.6 khz ? word length = 32 bit with this settings the reference clock freq uency is 2.9184 mhz = 32 * 2 * 45.6 khz. internal oscillator bb1_bck audio_in_abck clk_in osc_in osc_out adat3 blend dac256x encoder 2 osc_en clk_sel core clock pll peripheral clock pll pll settings clock to cores up to 166mhz clock to sdram up to 136 mhz (core in normal drive supply) up to 160 mhz (core in over drive supply) div2 sw application-controlled full - half frequency with 50% duty cycle clock to peripherals up to 70.56mhz (integer multiple of 44.1khz audio sampling rate)
STA680 operation and general remarks doc id 14860 rev 3 25/47 5.2 power on this chapter describes the power-on procedure for the cold start (cold start means that the device is completely disconnected from the power supply before being turned on). figure 9 and ta b l e 4 show the timing for the power up sequence of the cold start. figure 9. power on timing table 4. power on timing parameters symbol parameter min max unit t ramp-up external supply ramp-up time same ramp-up time for 3.3 v and 1.2 v supply - t dc1v8 dc1v8 regulator start-up time - 1 ms t osc (1) 1. oscillator start-up time depends on t he crystal connected to the internal oscillator. the given value is estimated for a crystal wi th these characteristics: oscillator start-up time - 400 s t rst reset release time 10 - s t cfg setup of clock/jtag configuration 0.1 - s core clock t dc1v8 t osc t rst t cfg primary boot min @ 2.9184mhz max @ 38.48mhz secondary boot @ 28.224mhz functional mode max @ 166mhz set for jtag /tap config . set for clock config . core supply (1.2v) i/os supply (3.3v or 1.8 v) ldo input supply (3.3v) ldo output supply (1.8v) osc_in osc_out reset_n adat adat2 adat3 blend dac256x t ramp - up ac00708
operation and general remarks STA680 26/47 doc id 14860 rev 3 figure 10. crystal characteristics 5.2.1 power supply ramp up phase all power supplies must be ramped-up to their specified levels within the time t ramp-up , set by the external power supply circuit on the board. the ramp up phase of each power domain should start at the same time. the reset_n pin must be kept low since the beginning. for normal applications, the testmode pin (factory test mode enable, see ta bl e 2 ) must be connected to ground. 5.2.2 oscillator setting time once the power supply has reached the operating level, the internal voltage regulator gets functional after t dc1v8 = 1 s (see ta bl e 4 ) and starts supplying the 1.8 v voltage to internal ips such as plls and crystal oscillator. the pll is powered up but not yet functioning since the internal logic keeps it in bypass mode until a stable clock is available and STA680 has entered the secondary boot phase. as shown in figure 9 , if an external crystal is connected to the internal oscillator this will output a correct waveform after t osc = 400 s (see ta bl e 4 ). at this time, if no crystal is used, a digital clock must be supplied according to the instructions detailed in section 5.1 . either if an external crystal is used or th e reference clock is provided through a digital source, the reset_n pin must be kept low for an additional t rst = 1.1 s. as described in section 5.1 the internal clock configuration is defined latching on the rising edge of the reset_n signal the value of the pins adat3, blend and dac256x; the value of this three signals must be stable at least t cfg = 0.1 s before the leading edge of the reset_n signal. 5.2.3 boot sequence once the reset_n signal has been released and the power up sequence correctly performed, the STA680 enters the boot procedure, which consists of two phases consisting of device setup and application authentication and download. during the first phase the STA680 executes the on-chip primary boot code contained in the 32 kilobyte boot rom. the primary boot synchronizes the internal cores, initializes the spi and iic interfaces and automatically selects the secondary boot code source by searching a pre-defined pattern into uart1, flash, spi1, iic1 and iic2. 38pf (33pf+5pf parasitic) ci=ci1=ci2 7pf co 26ff cm 1.33 mh lm 50 ohm rm model 38pf (33pf+5pf parasitic) ci=ci1=ci2 7pf co 26ff cm 1.33 mh lm 50 ohm rm model
STA680 operation and general remarks doc id 14860 rev 3 27/47 once the device on which the secondary bo ot resides has been found, following tasks are performed: the code is authenticated, the sdram is initialized and the secondary boot code is downloaded into it. the downloading speed depends on the device reference clock frequency even if this parameter does not have a big impact on the overall boot time since the dimension of this part of the code is small. during the second phase of the boot procedure to achieve acceptable boot time the STA680 performs plls setup and takes the internal clock frequency to 28.224 mhz (see figure 9 ) then downloads and validates the application code from the external flash memory. this last task ends the boot procedure. 5.2.4 normal operation mode after the execution of the boot code, the device enters the normal operation mode by jumping to the ma in program loop.
digital i/o and memory interfaces STA680 28/47 doc id 14860 rev 3 6 digital i/o and memory interfaces 6.1 interfaces: lqfp vs. lfbga the STA680 interface set depends on the package option selected, the lfbga giving the maximum flexibility where the lqfp package has a slightly smalle r set of interfaces, due to its smaller pin count. the differences between the two package options are detailed in ta b l e 5 . table 5. interface list interface name direction lqfp lfbga baseband interface 1 i ?? baseband interface 2 (data only) i ?? i 2 s audio input i ?? i 2 s audio output (six channels) o ?? i 2 c primary interface (micro) i/o ?? i 2 c secondary interface i/o x ? spi micro interface i/o ?? spi flash interface (double chip select) i/o ?? spi flash interface extension (up to 4 chip select) i/o x ? spi sd/mmc i/o x ? sdram interface i/o ?? s/pdif interface o ?? uart interface i/o ?? 4 gpio lines i/o x ? jtag test interface (boundary scan only) i/o ??
STA680 digital i/o and memory interfaces doc id 14860 rev 3 29/47 6.2 tuner interface the STA680 provides two digital baseband interfaces, named bbi1 and bbi2, through which the demodulated iboc signals can enter the hd radio decoder. the baseband tuner accepts the analog signal from the rf tuner, samples it, performs down conversion and filtering, and sends the zero-if signal across a baseband interface (bbi) to the STA680. using two interfaces the STA680 is able to decode two channels at the same time, allowing the implementation of features such as the background scanning of hd radio channels in search of traffic or weather information. the bbi consists of four-wires, 16 bit wide i and q data and two clocks. msb is always transmitted first. all signals are assumed to be zero-if. the native rate for fm is 744.1875 ks/s and for am it is 46.51171875 ks/s. sample rates of 650 ks/s, 675 ks/s, 882 ks/s and 912 ks/s are acceptable via the use of a sample rate converter. bbi2 is similar to bbi1 except bbi2 doesn?t have center filter so it is intended to be used for digital modulated signal only. for pin description refers to the ta bl e 5 . the data stream of the baseband interface varies depending on the mode selected. split mode splits i and q data onto the bb1_i and bb1_q pins, respectively. the rising and falling edges of bb1_ws mark the beginning of each i and q pair. multiplexed mode places the i and q data on to the bb1_i data pin. the falling edge of bb1_ws marks the start of the i data and the rising edge marks the start of q data. afe mode uses a single clock pulse on bb1_ws to indicate the start of i data followed by q data using the bb1_i pin only. figure 11 show signals waveform for the three modes. table 6. baseband interfaces pin list pin name designation type drive bb1_ws secondary base band interface word strobe i - bb1_bck primary baseband interface bit clock i - bb1_i primary baseband interface serial i data i - bb1_q primary baseband interface serial q data i - bb2_ws secondary baseband interface word strobe i - bb2_bck secondary baseband interface bit clock i - bb2_i secondary baseband interface serial i data i - bb2_q secondary baseband interface serial q data i -
digital i/o and memory interfaces STA680 30/47 doc id 14860 rev 3 figure 11. bbi waveforms and timings in ta b l e 7 are reported the timing values for the bb interface. i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 i15 i14 i13 i12 i11 ? ? i4 i3 i2 i1 i0 i15 i14 i13 i12 i11 ?? i4 i3 i2 i1 i0 q15 q14 q13 q12 q11 ... ... q4 q3 q2 q1 q0 q15 q14 q13 q12 q11 ? ? q4 q3 q2 q1 q0 sample n (i and q) sample n+1 (i and q) split mode bbx_ws bbx_bck bbx_i bbx_q sample n (i) sample n (q) sample n (i) sample n (q) bbx_ws bbx_bck bbx_i multiplexed mode i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 q15 q14 q13 q12 q11 ? ? q4 q3 q2 q1 q0 sample n (i) sample n (q) bbx_ws bbx_bck bbx_i afe mode ts th th ts th ts 2/fws 1/fws 1/fws 1/fbck,mux 1/fbck,split 1/fbck,afe ac00713 table 7. bbi timing values symbol parameter condition working rate unit min. max. fws word strobe - 650 675 744.188 882 912 khz fbck,split bit clock in split mode - 16 x fws - - - 66 mhz fbck,mux bit clock in multiplexed mode - 32 x fws - - - 32 x fws mhz fbck,afe bit clock in afe mode - 32 x fws - - - 66 mhz th data hold time - 4 - - - - ns ts data setup time - 8 - - - - ns
STA680 digital i/o and memory interfaces doc id 14860 rev 3 31/47 6.3 audio interface (aif) the aif (audio interface) is used for the communication with external digital signal sources and receivers. the main aif features are: 1 input sai interface. 3 output sai interface. 1 s/pdif transmitter. audio sample rate converter (asrc). i/o sample rates: 44.1 khz, 45.6 khz, 48 khz. the aif includes 1 input sai interface, 3 output sai interface and 1 s/pdif (industry standard) transmitter. the receivers and transmitters can be used either in master-mode, running with the STA680 internal audio frequency of 44.1 khz or in slave mode running with a frequency determined by the external device. in slave mode, in order to adapt the external data rate to the internal audio data rate, it is possible to use an internal audio sample rate converter (asrc, see chapter 6.3.4 ). 6.3.1 output serial audio interface (sai) the output serial audio interface is used to send decoded audio samples from the hd radio decoder to an external ic for audio processing, or directly to a digital power amplifier. the output sai is an i2s interface which provides audio samples in stereo at a 44,1 ks/s sample rate. other sample rates may be provided by means of the internal asrc (see chapter 6.3.4 ). the output sai interface shares the word strobe and the bit clock signal with three data output signals in order to support up to a total of 3 stereo channels of audio output. for interfacing the STA680 to an external dac an oversampling clock whose frequency is 256 times the sampling frequency is provided. for pin description refers to ta bl e 8 . the output sai supports a 32x or 64x bit cloc k. the 32x clock mode shifts out serial data with no padding. the 64x clock mode shifts out the 16-bit audio data first followed by 16 bits of zero padding. figure 12 shows timing diagrams for the supported modes. table 8. aif pin list pin name designation type drive audio_in_aws digital audio input word strobe i/o - audio_in_abck digital audio input bit clock i/o - audio_in_adat digital audio input serial data i - aws digital audio output word strobe i/o 4ma abck digital audio output clock i/o 4ma adat digital audio output serial data o 4ma adat2 digital audio output serial data channel 2 o 4ma adat3 digital audio output serial data channel 3 o 4ma dac256x digital audio output oversampling clock (256 x fs) o 4ma spdif digital audio output in spdif format o 4ma blend digital audio output blend output o 4ma
digital i/o and memory interfaces STA680 32/47 doc id 14860 rev 3 figure 12. serial audio interface waveforms and timings in ta b l e 9 are reported the timing values for the output sai interface. 6.3.2 input serial audio interface the input serial audio interface is used to receive the legacy am/fm demodulated samples from an external am/fm tuner for blending purpose. the input sai is an i2s interface which accepts 16 bit audio samples in stereo at a 44,100 s/s sample rate. other sample rates may be supported by means of the internal asrc. for pin description refers to ta b l e 8 . the input sai supports a 32x or 64x bit clock. the 32x clock mode shifts out serial data with no padding. the 64x clock mode shifts out the 16-bit audio data first followed by 16 bits of zero padding. figure 12 shows timing diagrams for the supported modes. 6.3.3 s/pdif interface the s/pdif interface is an output only. it is compliant to the standard iec 958 type ii. for pin description refers to ta b l e 8 . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 left right aws abck adat 32x mode (16 - bit data) d15 d14 d13 ? ? d3 d2 d1 d0 0 0 0 0 0d15 d14 d13 d3 d2 d1 d0 00 0 0 0 left right aws abck adat 64x mode (32 - bit data) ? ? 1/faws 1/faws 1/fabck,16 1/fabck,32 th ts ac00717 table 9. serial audio interface timing values symbol parameter condition working rate unit faws word strobe - 44.1 10 hz 45.6 15 hz 48 15 hz khz fabck,16 bit clock for 16-bit data - 32 x faws mhz fabck,32 bit clock for 32-bit data - 64 x faws mhz th data hold time - 5 ns ts data setup time - 20 ns
STA680 digital i/o and memory interfaces doc id 14860 rev 3 33/47 6.3.4 audio sample ra te converter (asrc) the STA680 supports various external host audio interfaces. the audio sample rate converter is designed to interface the audio output to systems with local master audio clock sources. output sample rates of 44,100 ( 10 hz), 45,600 ( 15 hz) and 48,000 ( 15 hz) are acceptable. total harmonic distortion plus noise (thd+n) at 1 khz is greater than 85 db down (0.0056%). one stereo channel (i.e. single adat line) either from the input sai or from the output sai can be used with the audio sample rate converter. in applications where the STA680 supplies the master clock to the audio d/a converter, the asrc will be bypassed. 6.4 serial peripheral interfaces (spi) the STA680 provides three serial peripheral interfaces, each one intended for a different and specific purpose: spi1 - the first spi is intended for communicating with the host microcontroller. alternatively to this purpose can be also the host micro i 2 c interface (see chapter 6.4.1 ) spi2 - the second spi has been taught to interface the STA680 with the external an external flash typically used to store the application code. spi3 - the third spi allow the hd radio deco der to control an external sd/mmc card. for master mode the spi clock frequency is a divide down by n of the internal peripheral clock frequency, where n is an integer number comprised between 2 and 65536. the maximum spi clock frequency in master mode is 25 mhz. for slave mode the maximum input frequency value accepted for the spi clock from an external device is a function of the internal peripheral clock. in particular the maximum frequency is , where f perif is the frequency of the clock feeding the peripheral bus and blocks figure 13 shows timing diagrams and waveform for the three spi. f spi f perif 8 -------------- - =
digital i/o and memory interfaces STA680 34/47 doc id 14860 rev 3 figure 13. spi interface timings diagrams and waveforms in ta b l e 1 0 are reported the timing values for the spi interface. 6.4.1 host micro serial peripheral interface (spi1) the host micro spi is used as a host processo r interface. the usage of this interface is optional because the STA680 is able to communicate with an external microcontroller also via i 2 c protocol (see chapter 6.4.5 , host micro i 2 c interface). the host micro spi is a slave only interface. for pin description see ta b l e 1 1 . table 10. spi interface timing values symbol parameter condition working rate unit min. max. tss chip select - 8/fsck - ns fsck serial bit clock, slave mode - 1.076 8000 khz fsck serial bit clock, master mode - 1.076 25000 khz th data hold time - 7 - ns ts data setup time - 15 - ns ac00718 d6 d5 d4 d3 d2 d1 d0 spix_sck cpol =0 ts th 1/fsck d7 z z spix_sck cpol =1 d6 d5 d4 d3 d2 d1 d0 d7 z z 1/fsck ts th tss spix_mosi/miso spix_mosi/miso spix_ss_n spix_sck cpha =0 d6 d5 d4 d3 d2 d1 d0 spix_sck cpol =0 ts th 1/fsck d7 z z spix_sck cpol =1 d6 d5 d4 d3 d2 d1 d0 d7 z z 1/fsck ts th tss spix_mosi/miso spix_mosi/miso spix_ss_n spix_sck cpha =1 table 11. host micro spi pin list pin name designation type drive spi1_miso host micro spi data master in/slave out o 4ma spi1_mosi host micro spi data master out/slave in i - spi1_sck host micro spi clock i 4ma spi1_ss_n host micro spi active-low slave select 1 i 4ma
STA680 digital i/o and memory interfaces doc id 14860 rev 3 35/47 6.4.2 flash serial peri pheral interface (spi2) the flash spi is useful for storing boot code and other configuration parameters. the minimum required capacity for this purpose is 1 mbit. the STA680 is spi master only on the flash bus. no glue logic is necessary to connect an external flash to the hd radio decoder. in the bga package up to 4 chips selects are available. for pin description see ta b l e 2 . 6.4.3 sd/mmc serial perip heral interface (spi3) the spi sd/mmc spi allows to connect the STA680 to a secure digital card or a multimedia card for data storage purposes. this interface can be configured to be master only and is available only in the bga package. for pin description see ta b l e 1 3 . 6.4.4 i 2 c interfaces the STA680 provides two i 2 c interfaces that can be used to communicate with the host microcontroller. the first one may be used by the host micro in replacement of the spi1 to control the main function of th e hd radio decoder. the second one is an auxiliary interface and is available only in the lfbga package option. for pin description see ta bl e 1 4 . table 12. flash spi pin list pin name designation type drive spi2_miso flash spi data master in/slave out i - spi2_mosi flash spi data master out/slave in o 4ma spi2_sck flash spi clock o 4ma spi2_ss_n flash spi active-low slave select 1 o 4ma spi2_ss1_n flash spi active-low slave select 2 o 4ma spi2_ss2_n flash spi active-low slave select 3 (1) 1. only available in bga package. o4ma spi2_ss3_n flash spi active-low slave select 4 (1) o4ma table 13. sd/mmc spi pin list pin name designation (1) 1. only available in bga package type drive spi3_miso sd/mmc spi data master in/slave out i 4ma spi3_mosi sd/mmc spi data master out/slave in o 4ma spi3_sck sd/mmc spi clock o 4ma spi3_ss_n sd/mmc spi active-low slave select 1 o 4ma
digital i/o and memory interfaces STA680 36/47 doc id 14860 rev 3 the data pins of the two i 2 c interfaces are open drain drivers and must have resistive pull- up conforming to philip's iic specification. figure 14 shows timing diagrams and waveform for the two i 2 c interfaces. figure 14. timing diagrams and waveform for the two i 2 c interfaces in ta b l e 1 5 are reported the timing values for the i 2 c interface. table 14. host and auxiliary i 2 c interface pin list pin name designation type drive iic1_scl host micro i 2 c interface serial clock line i/o 4ma iic1_sda host micro i 2 c interface serial data line i/o 4ma iic1_da (1) 1. only available in bga package. host micro i 2 c interface data acknowledged i/o 4ma iic2_scl auxiliary i 2 c interface serial clock line i/o 4ma iic2_sda auxiliary i 2 c interface serial data line i/o 4ma iic2_da (1) auxiliary i 2 c interface data acknowledged i/o 4ma ts,dat th,dat thigh iicx_sda iicx_scl bit 1 bit 2 bit n start stop 1/fscl tlow th,sta th,sto ac00719 table 15. i 2 c interface timing values symbol parameter condition standard-mode fast-mode unit min. max. min. max. fscl scl clock frequency - - 100 - 400 khz tlow low period of scl clock - 4.7 - 1.3 - s thigh high period of scl clock - 4 - 0.6 - s th,dat data hold time - 5 - - s ts,dat data setup time - 250 - 100 - s th,sta hold time for start condition - 4 - 0.6 - s ts,sto setup time for stop condition -4-0.6-s
STA680 digital i/o and memory interfaces doc id 14860 rev 3 37/47 6.4.5 host micro i 2 c interface (i2c1) the host micro i 2 c interface enables the host processor to pass commands, diagnostic information, and data between the host processor and hd radio decoder. the i2c1 interface is a standard i 2 c interface where the STA680 acts as a slave to the host micro and only responds to requests for information. it is also configurable by the host micro to work as a master to better support bi-directional flow of data and audio. the i2c1 interface supports 7-bit addressing and 8-bit data. it can run in both standard mode (serial clock frequency up to 100 khz) and fast mode (up to 400 khz). the i 2 c device addresses are reported in ta bl e 1 6 . although not part of the iic standard, an additional control line called iic1_da is provided. this line is useful for indicating when data is available and can be polled by either master or slave. 6.4.6 auxiliary i 2 c interface (i2c2) the auxiliary i 2 c interface can be programmed to be a master or slave. the usage of this interface by the host processor is optional and by default it is disabled after reset. the i2c2 interface supports 7-bit addressing and 8-bit data. it can run in both standard mode (serial clock frequency up to 100 khz) and fast mode (up to 400 khz). the i 2 c device addresses are reported in ta bl e 1 7 . although not part of the iic standard, an additional control line called iic1_da is provided. this line is useful for indicating when data is available and can be polled by either master or slave. table 16. i2c1 interface device address i2c1 primary address secondary address read address 0101111b 0101101b write address 0101110b 0101100b table 17. i2c2 interface device address i2c2 primary address secondary address read address 0101011b 0101001b write address 0101010b 0101000b
digital i/o and memory interfaces STA680 38/47 doc id 14860 rev 3 6.5 sdram interface the sdram interface supports up to 32m x 16 sdram and supports both standard and mobile protocols. for pin description see ta bl e 1 8 the minimum required sdram size for single channel application is 64 mbit while for a dual channel application at least 128 mbit are needed. figure 15 shows timing diagrams and waveform for the sdram interface. figure 15. timing diagrams and wa veform for the sdram interface in ta b l e 1 9 are reported the timing values for the sdram interface. table 18. sdram interface pin description pin name designation type drive sdr_d[0:15] sdram interface data bus i/o 4 ma sdr_a[0:12] sdram interface address bus o 4 ma sdr_ba[0:1] bank address o 4 ma sdr_cas_n active-low column address strobe o 8 ma sdr_ras_n active-low row address strobe o 8 ma sdr_we_n active-low write enable o 8 ma sdr_cs_n active-low chip select o 8 ma sdr_dqm0 low-byte data input/output mask o 4 ma sdr_dqm1 high-byte data input/output mask o 4 ma sdr_cke clock enable o 4 ma sdr_clk_ram3v3 clock to sdram for 3.3 v interface o 8 ma sdr_feed_clk feedback clock from sdram i 8 ma sdr_clk_ram sdr_cas sdr_a sdr_d sdr_ba sdr_we_n sdr_clk_cs sdr_ras row bank col bank din tos toh tih tis dout tcl tch tck bank bank row col cas latency = 3 write read
STA680 digital i/o and memory interfaces doc id 14860 rev 3 39/47 the frequency specification for the sdram interface depends on the supply condition of the core and on the software application. higher supply of the core allows higher speed on the sdram interface: core in normal drive: sdram interface works at a maximum speed of 136mhz when vddcore = 1.2v; core in over drive: sdram interface works at a maximum speed of 160mhz when vddcore = 1.4v for power saving and less interference on board, the sdram speed can be programmed to work at half speed respect to the internal data processing: full rate sw application: sdram interface works at the same frequency of the internal data processing; half rate sw application: sdram interface works at half frequency respect to the internal data processing table 19. sdram interface timing values symbol parameter condition software application min. max. unit tck scl clock period core in normal drive full rate 7.35 - ns half rate 12.05 - core in overdrive full rate 6.25 - half rate 12.05 - tch clk high level width - - 2.5 - ns tcl clk low level width - - 2.5 - ns toh data out hold time - - 0.9 - ns tos data out setup time - - 1.5 - ns tis data in setup time - - 0.8 - ns tih data in hold time - - 1.6 - ns tt transition time - - - 1.2 ns
electrical specifications STA680 40/47 doc id 14860 rev 3 7 electrical specifications 7.1 absolute maximum ratings 7.2 thermal data table 20. absolute maximum ratings symbol parameter value unit vdd core supply voltage 1.47 v vdd_gen_io generic io supply voltage 3.6 v vdd_fsh_io flash io supply voltage 3.6 v vdd_ram_io sdram io supply voltage 3.6 v vdd_osc osc 1v8 supply voltage 1.95 v vdd_pll_ana pll analog supply voltage 2.75 v vdd_pll_dig pll digital supply voltage 1.47 v vdd_saf saf core supply voltage 1.47 v v i voltage on input pin -0.5 to (vddio* + 0.5) v v o voltage on output pin -0.5 to (vddio* + 0.5) v t stg operative storage temperature -40 to +150 c t j operative junction temperature -40 to +125 c t amb operative ambient temperature -40 to +85 c table 21. thermal data symbol parameter lqfp lfbga unit r th j-amb thermal resistance junction-to-ambient (1) 1. according to jedec specif ication on a 4 layers board. 30 35 c/w
STA680 electrical specifications doc id 14860 rev 3 41/47 7.3 operating conditions table 22. dc electrical characteristics symbol parameter test cond ition min. typ. max. unit vdd core supply voltage normal drive 1.14 1.2 1.26 v over drive 1.33 1.4 1.47 v vdd_gen_io generic io supply voltage -3.03.33.6v vdd_fsh_io flash io supply voltage - 3.0 3.3 3.6 v vdd_ram_io sdram io supply voltage -3.03.33.6v vdd_osc oscillator analog supply voltage -1.71.81.95v vdd_pll_ana pll analog supply voltage -1.71.82.75v vdd_pll_dig pll digital supply voltage normal drive 1.14 1.2 1.26 v over drive 1.33 1.4 1.47 v vdd_saf saf supply voltage normal drive 1.14 1.2 1.26 v over drive 1.33 1.4 1.47 v idd_core (1) core supply current t amb =25c vdd=1.20v - 105 -ma vdd=1.26v - 110 -ma t amb = 85c vdd=1.20v - - 260 ma vdd=1.26v - - 280 ma idd_io (1) io supply current t amb =25c vdd_io (2) =3.3v - 40 -ma vdd_io=3.6v - 45 -ma t amb = 85c vdd_io=3.3v - - 55 ma vdd_io=3.6v - - 58 ma pd (1) power dissipation t amb =25c typical supply - 250 - mw t amb =85c max supply - - 600 mw iil low level input leakage current (3) vi = 0v - - 1.9 a iih high level input leakage current (3) vi = vdd_gen_io (4) --1.9a ilpu high level input leakage current on pull up (5) vi = vdd_gen_io (4) --2.9a ilpd low level input leakage current on pull-down (6) vi = 0v - - 10 a ipu pull-up current vi = 0v - - 72 a ipd pull-down current vi = vdd_gen_io (4) --72a
electrical specifications STA680 42/47 doc id 14860 rev 3 rpu equivalent pull-up resistance (7) vi = 0v 50 - - k rpd equivalent pull-down resistance (8) vi = vdd_gen_io (4) 50 - - k vil low level input voltage 3.3 supply mode -0.3 - 0.8 v vih high level input voltage 3.3 supply mode 2.0 - vdd_g en_io +0.3 v vhyst input hysteresis voltage 3.3 supply mode 50 - - mv voh output high voltage ioh =xma (9) vdd_r am_io ? 0.2v --v vol output low voltage iol =xma (9) --0.2v vesd electrostatic discharge voltage human body model - - 2000 v machine model - - 200 v charge device model - - 500 v ilatchup injection current maximum operating junction temperature 125 c 100 - - ma vdd_ram_io sdram io supply voltage -3.03.33.6v iil_ram low level input leakage current (3) vi = 0v - - - a iih_ram high level input leakage current (3) vi = vdd_ram_io - - - a ilpu_ram high level input leakage current on pull up (5) vi = vdd_ram_io - - - a ilpd_ram low level input leakage current on pull-down (6) vi = 0v - - - a ipu_ram pull-up current vi = 0v 44 122 a ipd_ram pull-down current vi = vdd_ram_io 29 122 a rpu_ram equivalent pull-up resistance (7) vi = 0v 29 67 k rpd_ram equivalent pull-down resistance (8) vi = vdd_ram_io 29 103 k vil_ram low level input voltage - 0.8 - - v vih _ ram high level input voltage - - - 2 v vhyst_ ram schmitt trigger hysteresis - 300 - 800 mv table 22. dc electrical characteristics (continued) symbol parameter test cond ition min. typ. max. unit
STA680 electrical specifications doc id 14860 rev 3 43/47 voh_ ram high level output voltage ioh = -xma (9) vdd_r am_io -0.3 --v vol_ ram low level output voltage iol =xma (9) --0.3v 1. current consumption and power diss ipation measured for singl e channel software application running at 127mhz. 2. vdd_io = vdd_gen_io + vdd_fsh_io + vdd_ram_io. 3. performed on all the input pins ex cluded the pull-down and pull-up ones. 4. vdd_gen_io may be vdd_fhs_io or vd d_gen_io depending on interface considered. 5. performed only on the input pins with pull up. 6. performed only on the input pins with pull down. 7. guaranteed by ipu measurements. 8. guaranteed by ipd measurements. 9. xma = 4ma for a bd4, 8ma for bd8 pad type. table 22. dc electrical characteristics (continued) symbol parameter test cond ition min. typ. max. unit
package information STA680 44/47 doc id 14860 rev 3 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 16. lqfp144 (20x20mm) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.8740 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 17.500 0.6890 e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 17.500 0.6890 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0?(min.), 3.5?(typ.), 7?(max.) ccc 0.080 0.0031 lqfp144 (20x20x1.40mm) l ow profile plastic q uad f lat p ackage note 1: exact shape of each corner is optional. 0099183 c
STA680 package information doc id 14860 rev 3 45/47 figure 17. lfbga 168 balls (12x12x1.4 mm) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.400 0.0551 a1 0.210 0.0083 a2 0.200 0.0078 a4 0.800 0.0315 b 0.350 0.400 0.450 0.0138 0.0157 0.0177 d 11.850 12.000 12.150 0.4665 0.4724 0.4783 d1 10.400 0.4094 e 11.850 12.000 12.150 0.4665 0.4724 0.4783 e1 10.400 0.4094 e 0.800 0.0315 z 0.800 0.0315 ddd 0.100 0.0039 eee 0.150 0.0059 fff 0.080 0.0031 lfbga 168 balls l ow profile f ine pitch b all g rid a rray 8123111 b body: 12 x 12 x 1.4mm
revision history STA680 46/47 doc id 14860 rev 3 9 revision history table 23. document revision history date revision changes 25-jul-2008 1 initial release. 19-dec-2008 2 update ecopack ? information in section 8 on page 44 . 31-jul-2009 3 added section 2: hd radio? system on page 7 . changed ta b l e 2 , 4 , 7 , 12 , 13 , 14 , 19 and 22 . changed figure 4 , 5 , 6 , 7 , 8 and 13 . add figure 10: crystal characteristics on page 26 .
STA680 doc id 14860 rev 3 47/47 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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